ASIC: Gate Arrays, Embedded Arrays and Standard Cells

The Three Types of SANYO ASIC

SANYO provides three types of ASIC that differ in the manufacturing processes used.
This variety allows us to provide our customers with optimal ICs for their needs.

Gate Arrays (GA):LC24xxx, LC22xxx Series

Short development period
Development costs can be minimized

Gates are arranged in advance in an array structure on the chip.
These gates are then connected using metal interconnects to form logic circuits.
Support for 0.6µm 0.35µm product series

Gates (based on gates that consist of 4 transistors) are arranged on the chip in an array structure (SOG) in advance, and are connected by metal interconnects to form logic circuits.
The fabrication process consists solely of forming the metal interconnects, allowing this series to support quick development.

Embedded Arrays (EA):LC273xx, LC272xx, LC27xxx Series

Supports short development periods
High degree of design flexibility
Effective from a mass production cost standpoint

First, the number of gates and the type and number of megacells are determined.
The megacells are arranged on the master.
Other areas have the same structure as gate arrays, and the masters are stocked prior to the interconnect process.
After logic verification, the IC is completed in the same way as gate arrays, i.e. by the formation of metal interconnects.
SANYO provides an extensive set of megacells.
Support for 0.6µm, 0.35µm, 0.25µm, 0.18µm product series

In embedded array development, first the customer determines the overall IC design, the number of gates required, and the types of the required megacells. Then, development proceeds to the master creation stage. In the master, the megacells are arranged on the chip, and all other areas are set up identically to gate arrays, i.e. in an SOG configuration.

These masters are stocked in the pre-interconnect state, and await logic verification. After logic verification, the IC is completed in the same manner as gate array products, i.e. by the formation of the metal interconnects. Embedded cell development allows ICs with functionality equivalent to standard cell ICs to be developed in the same short development time as that achieved by gate array development.
The development period can be shortened since development only consists of modifying the logic blocks and the interconnect process.

SANYO provides an extensive set of megacells for these ASICs.

Standard Cell (SC):LC98700, LC98600, LC98500, LC98300 Series

High degree of design flexibility
Effective from a mass production cost standpoint

ICs are completed by arranging and connecting specially designed function cells and previously provided megacells.
Megacells with even higher levels of functionality can also be included.
SANYO provides an extensive set of megacells.
Support for 0.6µm, 0.35µm, 0.25µm, 0.18µm product series

Standard cells are ICs that are created by combining megacells that are provided in advance and specially designed function cells. With this technique the development period is somewhat longer than that required by gate array and embedded array designs since specially designed functions are created from the base wafer. However, not only does this technique provide higher integration densities, it also supports the use of even more powerful megacells.