ASIC: Gate Arrays, Embedded Arrays and Standard Cells
ATPG Full Scan Support
Due to the increasing scale of contemporary ICs, a high fault coverage is seen as a necessary condition to assure IC reliability. However, extensive efforts are required to create test patterns that provide a high fault coverage.
To ameliorate this problem, we have introduced ATPG (automatic test pattern generation) and full scan (see figure below) as design for testability technologies. These technologies can significantly ease the efforts required of the customer in test pattern creation. Normally, two dedicated pins are required to embed a full scan function, and the gate count increases as well.
- Features
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- Scan design rule checking, scan circuit conversion, and test pattern generation are all automatic.
- Automatic achievement of a high fault coverage