ASIC: Gate Arrays, Embedded Arrays and Standard Cells
CAD Tools
1: Interface Support for CAD Tools
SANYO provide interface support for the following CAD tools for SANYO ASIC development.
| Functional verification (RTL) | Verilog-HDL | Verilog-XL, NC-Verilog, VCS |
|---|---|---|
| VHDL | ModelSim, NC-VHDL | |
| Logic synthesis | Design Compiler, BuildGates | |
| Logic circuit entry tools | ViewDraw (Powerview,WarkviewOffice) | |
| Logic verification (Gate Level) |
Verilog-HDL | Verilog-XL, NC-Verilog, VCS |
| VHDL | ModelSim, NC-VHDL | |
| Others | ViewSim (Powerview,WorkviewOffice) | |
| Timing verification (Gate Level) |
Verilog-HDL | Verilog-XL, NC-Verilog, VCS |
| VHDL | ModelSim, NC-VHDL | |
| Others | ViewSim (Powerview,WorkviewOffice) | |
| FPGA conversion | MAX+plus II, Foundation | |
- VCS and Design Compiler are registered trademarks of Synopsys.
- ViewDraw and ViewSim are registered trademarks of Mentor Graphics Corporation.
- Verilog-XL, NC-Verilog, NC-VHDL and BuildGates are registered trademarks of Cadence Design Systems.
- Model Sim is a registered trademark of Model Technology.
- MAX+plus II is a registered trademark of Altera Corporation.
- Foundation is a registered trademark of Xilinx, Inc.
2: Toolkit Loan Service
SANYO will loan an ASIC development support toolkit (consisting of a PC, CAD tools, and a design toolkit) to customers who do not own CAD tools.
Customers can develop SANYO ASICs using this toolkit.
| PC | [750 MHz Pentium III with 768 MB RAM] |
|---|---|
| Software | Entry tool, simulator ASIC design kit (library and utility software) |
3: Development Environment
The following front end system tools are used in SANYO's ASIC development environment.
| RTL checker | RTqualify | |
|---|---|---|
| DFT checker | Turbo Check | |
| Functional verification (RTL) | Verilog-HDL | Verilog-XL, NC-Verilog, VCS |
| VHDL | ModelSim, NC-VHDL | |
| Formal inspection | 0-In Check, 0-In Search | |
| Logic synthesis | Design Compiler, BuildGates | |
| Physical synthesis | Physical Compiler | |
| Static timing analysis | PrimeTime | |
| Formal verification | INCISIVE CONFORMAL | |
| Logic circuit entry | ViewDraw (Powerview,WorkviewOffice) | |
| Test simplification design | DFT Compiler, TestGen, BSD Compiler, MBIST Architect, TetraMAX | |
| Logic verification (Gate Level) |
Verilog-HDL | Verilog-XL, NC-Verilog, VCS |
| VHDL | ModelSim, NC-VHDL | |
| Others | ViewSim (Powerview,WorkviewOffice) | |
| Timing verification (Gate Level) |
Verilog-HDL | Verilog-XL, NC-Verilog, VCS |
| VHDL | ModelSim, NC-VHDL | |
| Others | ViewSim（Powerview,WorkviewOffice） | |
| Power improvement and analysis | Power Compiler | |
| FPGA conversion | MAX+plus II, Foundation | |
| Fault simulation | TurboFault, Verifault-XL | |
- VCS, Design Compiler, PrimeTime, DFT Compiler, TestGen, BSD Compiler, TetraMAX, Physical Compiler, Power Compiler, Design Power are registered trademarks of Synopsys.
- ViewDraw, ViewSim, MBIST Architect, 0-In Chek and 0-In Search are registered trademarks of Mentor Graphics Corporation.
- Verilog-XL, NC-Verilog, Verifault-XL, NC-VHDL and BuildGates are registered trademarks of Cadence Design Systems.
- ModelSim is a registered trademark of Model Technology.
- INCISIVE CONFORMAL is a registered trademark of Verplex.
- MAX+plus is a registered trademark of Altera Corporation.
- Foundation is registered trademark of Xilinx, Inc.
- TurboFault and TurboCheck are registered trademarks of Syn Test Technologies.
- RTqualify is a registered trademark of HDLab.