ASIC: Gate Arrays, Embedded Arrays and Standard Cells
Signal Integrity: Preventing the Occurrence of Crosstalk Problems
Crosstalk problems are of much concern due to the increased coupling capacitances between lines associated with higher integration densities.
*In SANYO ASICs, extensive workarounds and verification are applied in the layout process, not only to clock and reset lines, but to ordinary signal lines as well, to eliminate these problems in the actual chip.
Power Integrity: Increasing Reliability
The danger of operational failures due to electromigration and chip internal voltage drops (IR drop) increases in highly-integrated large-scale ICs.
In SANYO ASICs, a power supply analysis is applied to the whole chip, and an optimal power supply network is designed to prevent these problems.
