ASIC: Gate Arrays, Embedded Arrays and Standard Cells
Clock Skew Management
Clock skew is a major problem in the design of large-scale high-speed ASICs. SANYO supports layouts that use a dedicated clock trunk line or CTS to resolve this clock skew problem.
Clock Tree Synthesis (CTS)
As shown in the figure, buffer insertion and layout and flip-flop layout is performed to minimize clock skew in the chip.
