ASIC: Gate Arrays, Embedded Arrays and Standard Cells
ASIC Development Procedure
System Design
The gate scale of the part of the system to be implemented as an ASIC and the number of I/O pins are used in selecting the required operating speed, the master chip (either a gate array or an embedded array), and the package.
Wafer sign-off
This step only applies to embedded array development. The master wafer is committed at the point we get approval from the customer. Note that wafers are stocked at the step prior to the interconnect process and await logic verification of the entire circuit.
Logic circuit diagraminput and test design
The logic circuit diagram and the test data that were created are inputted to the entry tool. At this time, whether or not the design rules were followed is checked.
Functional simulation
Whether or not the RTL HDL notation operates correctly at the functional level is checked. Here, input stimulus are created according to the rules, and a functional simulation is performed.
Logic synthesis and test design
Logic data that depends on the technology used by SANYO is created in accordance with the design constraint conditions such as the operating clock frequency, the chip size, the PVT variations, and the I/O timing using the technology libraries supported by SANYO.
Floorplanning
A layout image in module units is created using a floor planner. Then units that have complex connections between modules are grouped and the chip layout is determined.
Virtual delay simulation and fault simulation
Virtual delay data is created and the fanout is checked. Then, the process moves to the virtual delay simulation stage. Additionally, a timing analysis of the setup, hold, and other times is performed.
Also, the fault coverage is calculated based on the test data.
Static timing verification, power dissipation calculation, and design for testability
In the static timing verification step, the timing can be verified without using the test pattern. In the power dissipation calculation step, the power can be estimated from the simulation execution log. In the design for testability, replacement by scan cells and automatic test pattern generation are performed.
First sign-off
At the point that the unit delay simulation and virtual delay simulation have been completed, once we have approval from the customer we can proceed to layout work.
Layout
Chip layout is performed based on the I/O cell placement data, the circuit connection description data, etc. The layout period will be somewhat longer in cases where measures are required to handle clock skew.
Actual delay simulation
An even more precise simulation and timing analysis are performed using the delay data derived from the layout data. The customer then verifies the result of the actual delay simulation (the post-layout simulation). When this stage is complete, SANYO provides an ASIC design specifications document to the customer.
Second sign-off
At this stage, the customer verifies the contents of the ASIC design specifications document. The mask data begins to be created with the approval of the customer.
Test production
After the second sign-off, when the customer has verified the contents of the ASIC design specifications document, the mask data is created and SANYO begins test production of the IC.