ASIC: Gate Arrays, Embedded Arrays and Standard Cells
Floorplanning
Floorplanning is a technique that allows layouts that are efficient both from timing and integration density standpoints to be designed by dividing the circuit into functional blocks and taking the flow of signals between blocks and the wiring density into account.
ECO
This technique applies to designs for which the layout and timing verification have been completed. The layout data that has already been completed is saved and only the sections to be changed are laid out again.
As opposed to performing a complete re-layout, this holds the efforts required for timing verification to a minimum.
