ASIC: Gate Arrays, Embedded Arrays and Standard Cells
User Interface Levels
SANYO provides four user interface levels, from functional specifications to mask data, so that the ASIC development
process will proceed smoothly.
The development period and cost are determined by the interface level chosen by the customer.
- LEVEL SInterface starting with system design
- Here, the customer determines only the functional specifications of the IC. SANYO develops the IC based on those specifications.
- LEVEL 0Interface starting with the user specifications circuit diagram
- Here, the customer provides SANYO only with a logic circuit diagram or an RTL functional description file. SANYO performs all development steps starting with test data creation.
- LEVEL 1Interface starting with the SANYO format circuit diagram and test data
- Here, the customer handles the design process through logic circuit diagram and test data creation. From that point, SANYO works together with the customer up to the gate level virtual delay simulation step. If language design is used, the customer handles the steps through functional simulation.
- LEVEL 2Interface starting with the post-simulation data
- Here, the customer performs all steps through virtual delay simulation. SANYO can provide tools that enable the customer to achieve a level 2 interface.