ASIC: Gate Arrays, Embedded Arrays and Standard Cells
Timing Care
As circuits get larger and faster, the chances of timing errors occurring after layout and interconnection increase. The development TAT can be shortened by “taking care”, that is, by using a specialized step that semiautomatically checks the waveform degradation, setup, and hold conditions.
Physical Compiler
SANYO has introduced the use of a “Physical Compiler” for the timing convergence step, a step that, until now, has required large amounts of designers' time.
This physical compiler can shorten the design period significantly. Using the physical compiler, the designer can automatically acquire layout results and a netlist with no timing violations by performing logic synthesis and layout at the same time.
