ASIC: Gate Arrays, Embedded Arrays and Standard Cells
Layout Design for Ultra-Deep Submicron Processes
SANYO ASIC products allow the design of high-performance highly integrated ICs fabricated in ultra-deep submicron processes.
Timing Integrity: Preventing the Occurrence of Timing Problems
This tool uses a high-precision three-dimensional RC extraction based method to calculate the amount of delay in the interconnects, a calculation that is increasingly important in processes with finer rule sizes.
Timing optimization is performed at each of the floorplan, layout, and interconnect processes to achieve the fastest IC operation possible.
Layout is performed at the same time as logic synthesis to provide a synthesis environment that achieves both high performance and high integration densities.
