Flash Memory/EEPROM

Comparison of Cell Structure

Typical Stacked-gate Structure

EEPROM generally employ a stacked-gate cell structure. Data is retained by controlling an electric charge stored in the floating gate (FG) in the memory cell.

"Susceptible to Over-Erasure Problems"
Over-erasure may occur if the FG becomes unstable.

Thus, the charge in the FG must always be kept under a specific level, and weakening of the charge during long-term data retention is a concern. There are also concerns from the complexity of the control circuit structure and the larger scale of peripheral circuits.

Split-gate Cell Structure from SANYO

SANYO EEPROM employ a split-gate cell structure. In a split-gate cell, the drain side is under the gate, and this suspended portion fulfills the role of a select gate.

"Advantage: No Over-Erasure"
Regardless of the FG potential, the structure prevents cell current (Ir) from flowing when the gate is not selected.

1 cell (split-gate cell) = 1 Tr + stacked-gate cell structure

Comparison of Reliability

Typical Cell Structure

Because over-erasure problems may occur, there is an upper limit to potential on the data erasure side.

SANYO Cell Structure

Because no over-erasure problems can occur, there is no upper limit to potential on the data erasure side.For this reason, an ample difference between the potentials for erasure data and for program data can be ensured,offering a wider data retention margin than in the memory devices of other manufacturers.

SANYO Cell Advantages

WL SL BL WL SL BL
Erase 0V Vee Open Vee 0V 0V
Erase Time A few seconds 25ms
Program Vpp 0V Vcc 2V Vpp 1V
Program Time 10µs 10µs
Program Current On the order of mA 2 to 3µA

Flash products are licensed from Silicon Storage Technology, Inc., (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.

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